Error reporting in computer systems generally takes up many interconnect lines and inefficiently utilizes multiple clock domains. In particular, PCI Express™ protocol error handling involves errors in all three layers (physical, link, and transaction layers) and there is a different clock domain and separate interconnect lines for each layer. Currently, there must be an error handling block for each PCI Express™ layer. The multiple error handling blocks create redundant logic, increase the number of interconnect lines utilized for logging errors in the device/function configuration space, and slow down error transactions because the clock domains are not synchronized.